The present invention relates to a pattern forming method, more specifically to a pattern forming method suitable for forming a multi-level interconnection layer on a substrate with LSI chips embedded in.
With requirements of higher performance and smaller sizes of electronic equipments, input and output densities of semiconductor devices are on increase. It is proposed to use, as LSI packages, packages, such as CSP (Chip Size Package) and wafer-level CSP, etc., which can be smaller-sized. As substrates for these small-size packages to be mounted on, multi-layered resin substrates formed of plurality of interconnection layers and resin insulating layers alternately laid one on the other are proposed.
Recently is proposed a method in which a multi-level interconnection layer is formed on a substrate with LSI chips embedded in instead of mounting LSI chips onto a package substrate in the above-described method. The package substrate prepared by this method has advantages of small inductances and decreasing stresses generated by heat. A further advantage is that interconnections can be increased, and various electronic and optical devices, such as logic LSI, memory LSI, RF, MEMS (micro electromechanical systems), etc., can be built in. Furthermore, the package substrate has higher interconnection freedom and good electric power supply performance, and is suitable to incorporate inter-layer dielectric material of low dielectric constant.
Then, the method for fabricating the conventional package substrate, in which a multi-level interconnection layer is formed on a substrate with LSI chips embedded in will be explained with reference to FIGS. 6A-6C.
LSI chip 102 is embedded in a mold frame of a core substrate 100 of BT (bismaleimide triazine) resin, etc. (FIG. 6A).
Next, a sealing resin 104 is filled into the gaps between the core substrate 100 and the LSI chip 102 to thereby secure the LSI chip 102 to the core substrate 100 (FIG. 6B).
Then, on the core substrate 100 with the LSI chip 100 embedded in, insulating layers 106, 110, 114, 118 and interconnection layers 108, 112, 116 are alternately laid into a multi-level interconnection layer 120 in the same way as in the method for forming a built-up layer in the conventional packaging technique (FIG. 6C).
The package substrate with the multi-level interconnection layer 120 connected to the LSI chip 102 can be thus formed on the core substrate 100.
However, according to the above-described method for fabricating the conventional package substrate, in which a multi-level interconnection layer is formed on a substrate with LSI chip embedded in, a plurality of LSI chips embedded in a core substrate are often independently disaligned. In such case, patterning of via holes and interconnection layers by using a glass mask or a reticle with a prescribed pattern formed on cannot form the multi-level interconnection layer in accurate alignment with the respective LSI chips.
This has required very high alignment accuracy in arranging the LSI chips. Higher accuracy for the alignment is required for a larger number of LSI chips, which makes it difficult to control the alignment accuracy.
Even when LSI chips are secured to a core substrate with high alignment accuracy, the alignment accuracy is often degraded due to a thermal expansion coefficient difference with respect to the sealing resin.
In forming a multi-level interconnection layer, when pattern distortions and shrinkages take place due to thermal processing, it often makes it difficult to align a pattern of a layer to be formed thereon.